I don’t know if I’m using the right vocabulary, maybe “die size” is the wrong way to describe it. But the Ultra line packages two Max SoCs with a high performance interconnect, so that the whole package does use about 1000 mm^2 of silicon.
My broader point is that much of Apple’s performance comes from their willingness to actually use a lot of silicon area to achieve that performance, and it’s very expensive to do so.
You could say total die size, but you wouldn’t say die, that implies a single cut exposure of silicon.
But agreed, Apple just took all the tricks Intel dabbled with and turned them to 11, Intel was always too cheap because they had crazy volumes (and once upon a time had a good process) and there was no point.
I don’t know if I’m using the right vocabulary, maybe “die size” is the wrong way to describe it. But the Ultra line packages two Max SoCs with a high performance interconnect, so that the whole package does use about 1000 mm^2 of silicon.
My broader point is that much of Apple’s performance comes from their willingness to actually use a lot of silicon area to achieve that performance, and it’s very expensive to do so.
You could say total die size, but you wouldn’t say die, that implies a single cut exposure of silicon.
But agreed, Apple just took all the tricks Intel dabbled with and turned them to 11, Intel was always too cheap because they had crazy volumes (and once upon a time had a good process) and there was no point.